1. Field of the Invention
The invention relates to an apparatus for processing signals, in particular physiological measuring signals, for instance EEG-signals (electroencephalogram signals), wherein the apparatus is provided with a plurality of channels with signal inputs for receiving input signals, which input signals each comprise a specific signal component and a signal component common to all input signals (also called a “common mode” signal), wherein each channel is provided with an impedance transforming input amplifier, wherein the apparatus is configured for supplying to a first input of each input amplifier a respective signal and to a second input an analogue reference signal which is equal for all channels.
2. Description of the Related Art
Such an apparatus is known from international application WO2009/017413, the content of which is incorporated by reference in its entirety. As follows from this publication, it has appeared that with particular measurements, for instance electrophysiological measurements, the input signals (E1, E2, E3, . . . , En,) can each contain various components.
A first component in each signal comprises, in particular, the electrophysiological information. A second component comprises, in particular, a mains interference signal. A third component comprises a sensor offset signal (in particular an electrode offset signal).
The electrophysiological information mentioned is in particular the important measurement part of the input signal and can have an amplitude in the range of, for instance, some microvolts to some millivolts.
Mains interference, in particular resulting from 50 Hz or 60 HZ mains AC voltage, is also called a “common mode disturbance”. The amplitude of this interference can vary strongly, between, for instance, 1 and 100 mV.
A sensor-offset signal, in particular an electrode offset (the third component in an input signal) can have varying amplitudes, and is generally not stable. It can comprise a DC signal with an amplitude between 0 V and some hundreds of mVs, and can vary with a very low frequency.
An example of the know reference amplifier is depicted in FIG. 1. As follows from FIG. 1, a known compensated digital DC reference amplifier serves for processing signals, in particular physiological measuring signals supplied through sensors (not represented), and is provided with several (N) channels with N signal inputs 1 for receiving input signals. The input signals E1, E2, E3, . . . , En (with n being 1, 2, 3, . . . , N) each comprise a specific signal component and a signal component common to all input signals (the “common mode signal”). As follows from the above, the specific signal component may include an electrode signal as such, the electrode signal particularly including the afore-mentioned electrophysiological information and electrode offset signal.
Thus, for a particular period of time, one or more input signals E1, E2, E3, . . . , En can contain sensor related offset signal parts. Each channel is provided with an impedance transforming input amplifier 3. These amplifiers 3 are preferably operational amplifiers (Opamps). The apparatus is also provided with a digital signal processor 210, and several analogue-digital converters (A/D converters) 5, i.e. one per channel, for supplying the amplified signals provided by the input amplifiers 3, to the digital signal processor 210. The signal processor 210 is designed for converting signals received from the one or more analogue-digital converters 5 into at least one or more output signals, and outputting this/these, for instance, via a signal output 219. The signal processor 210 may be provided with, for instance, one or more other inputs, for instance a serial input 221 for communication with other modules or components.
The known apparatus is provided with low pass filters 7. An input of each filter 7 may be directly or indirectly coupled to the output of a respective input amplifier 3, of the same channel, for receiving the signal coming from this amplifier.
Following from WO2009/017413, the signal processor 210 may be designed for supplying a digital reference signal, which digital reference signal is converted into said analogue reference signal Vref by suitable converter means 111, 6a. In particular, the digital signal processor 210 may be designed to process, in particular digitally average, the digital signals received from the A/D converters 5, for providing the digital reference signal. Said averaging comprises, for instance, a summation step Σ wherein the digital signals, coming from the N different channels, are added up, and a division step 1/N wherein the sum of the digital signals (i.e. the result of said summation step) is divided by the number N of those signals (i.e. the number of channels). The digital result of this operation comprises a digital reference signal, which is supplied via a signal output to a digital-analogue (D/A) converter (DAC) 111 (for instance a 20 bit D/A converter 111). This D/A converter 111 converts the digital reference signal into an analogue signal, which analogue signal is processed via an impedance transforming amplifier 6a for providing the analogue reference signal Vref. To this end, the output of the D/A converter 111 is coupled via a suitable impedance (in particular comprising a resistance m) to the first input (e.g. the non-inverting input) of this amplifier 6a, while the other (e.g. the inverting) amplifier input is electrically short-circuited to the amplifier output. As follows from the drawing, the analogue reference signal Vref is fed to only one of the inputs if each input amplifier 3 (i.e. only to the first input, and not to the second input).
In addition, the apparatus includes a second amplifier stage, comprising compensation amplifiers (in particular Op amps) 212 which are each arranged in a respective channel between a low pass filter 7 and A/D converter 5. In particular, a first input of each compensation amplifier 212 is arranged for receiving the low pass filtered amplified signal from a respective input amplifier 3, via a filter 7. An output of each compensation amplifier is directly coupled to an A/D converter 5 for providing a signal compensated by the amplifier 212 to the A/D converter 5, wherein the A/D converter supplies the digitized signal to a respective input (In) of the signal processor 210.
In the know apparatus, the second input of each compensation amplifier 212 is coupled via a suitable digital-analogue converter 213 to a respective output (Out) of the signal processor 210 for receiving a control signal therefrom. In this case, the signal processor 210 comprises, for instance, a microcontroller, with suitable software for carrying out various signal processing functions of the signal processor 210. These signal processing functions comprise, in particular: calculating a digital reference signal, producing suitable control signals to be supplied to the D/A converters 213 and providing output signals, via the (preferably serial) output 219. The signal processor 210 is designed for providing each control signal under the influence of and/or while utilizing one or more digital signals obtained from the analogue digital converters 5.
Following from WO2009/017413, the elaboration according to FIG. 1 has several advantages. For instance, a relatively high gain may be used, for instance 500× (for instance 10× in the input stage 3 and 50× in the compensation stage 212, or a different, suitable proportion), so that A/D converters 5 with a relatively low resolution, low disturbance, high sample frequency and virtually no delay may be used.
The publication “A Bio-Signal Amplifier System with Very-Large Dynamic-Range”, Robert Rieger et al., Tencon 2007 IEEE region 10 conference, IEEE, 30 Oct. 2007 pages 1-4, describes the recording of very small signals such as body potentials, wherein a single amplifier is reset before it can leave its dynamic range. The feedback provided is not continuous. In FIG. 4 of the document, a discrete level offset is fed to both inputs of an OPAMP. Besides, the electrode signal is fed to both inputs of the OPAMP. According to the document, the sole purpose of the compensation voltage is to ensure that the amplifier always works within its intended operating region; removal of any residual offset is not required. A similar system and method is disclosed in U.S. Pat. No. 5,205,294.
WO2008/080008 discloses an operational amplifier circuit for conditioning analogue bioelectric signals, wherein both the inverting and non-inverting terminal are coupled to a common reference potential. A common reference potential can be generated inside an acquisition system, wherein a subject can be biased to the same potential.
The publication “Highly sensitive biomedical amplifier with CMRR calibration and DC-offset compensation”, Eurocon 2009, IEEE, Piscataway N.J. USA, May 18, 2009 pages 152-155 discloses application of a switchable resistor array of a digitally controlled calibration circuit, for increasing a common mode rejection ratio. Electrode signals are fed to the non-inverting input of a amplifier, whereas both a common reference voltage and a dc-offset compensation voltage (Vdac) are fed to the inverting input. Due to the fact that mutually different Vdacs will be present in the different channels, so that amplification for each channel regarding the common mode signal will be different. It is required that a number of resistors are calibrated for each channel, to obtain a desired common mode rejection.